(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an electrostatic discharge device using shallow trench isolation technology in the fabrication of integrated circuits.
(2) Description of the Prior Art
Electrostatic discharge (ESD) refers to a high voltage accidentally applied to an integrated circuit. ESD can result from either automated or human handling. If the voltage applied to the gate insulator becomes excessive, the gate oxide can break down. MOSFET devices are particularly vulnerable to ESD damage. Because of this danger, ESD protection transistors are fabricated to direct ESD current away from the circuit it is protecting.
Shallow trench isolation (STI) is widely used in integrated circuit manufacturing. One conventional STI process is illustrated in FIGS. 1-3. Referring to FIG. 1, there is shown a trench etched into the semiconductor substrate 10. The trench is filled with a dielectric layer 12 by any of a variety of gap-filling methods. In order to avoid dishing of the STI region during polishing, such as by chemical mechanical polishing (CMP), a reverse trench mask 15 is formed over the trench. Most of the dielectric layer 12 is etched away where it is not covered by the mask 15. The mask is removed and the dielectric layer is planarized to the surface of the substrate, as shown in FIG. 3.
The present invention uses a method similar to this STI technology to form an ESD device.
A number of patents present a variety of methods to form ESD devices. U.S. Pat. No. 5,629,544 to Voldman et al teaches forming an ESD gate partially over an STI region. U.S. Pat. No. 5,744,841 to Gilbert et al shows a halo region around the source and/or drain to optimize breakdown voltage and shows an ESD gate over a field oxide regions. U.S. Pat. No. 5,918,117 to Yun shows a method of forming an ESD device. U.S. Pat. No. 5,885,875 to Hsu discloses an ESD device over a field oxide region and an ESD implant under the field oxide region.